1. Field of the Invention
The present invention relates to a method and apparatus for controlling a dual bus system used by high reliability computers (fault tolerant computers) or the like.
2. Description of the Related Art
Technique for realizing high reliability of computers is known as described in U.S. Pat. No. 4,484,273 entitled "MODULAR COMPUTER SYSTEM". According to this related background art, a plurality of processors, memories and bus adapters in a computer system are connected to a dual bus system and to interface units connecting the buses. Of the dual bus system, an executive bus operates at normal times. A non-executive bus stands by or operates as another access path to improve the system throughput.
Another background technique for realizing high reliability of computers is described in "Nikkei Electronics", May 9, 1983 Issue, at pp.197 to 202. This background art uses a method called a pair-and-spare method which is characterized in that each logical unit has a pair of partner boards operating at a lock-step. If one of the pair boards becomes faulty, it is disconnected to allow a continuous operation of the other correct board, without intervention by the operating system.
In the dual bus system of the first background art, it is necessary to regularly patrol the standby bus so as to check the soundness of it. This check necessarily requires support by the software. If the patrol period is made short in order to improve the check precision, the system performance is degraded. If one of the buses of the dual bus system is used as another access path, support by software is required for the case of a failure of the other of the buses, and the system performance is considerably degraded.
The second background art using the pair-and-spare method eliminates the above-described disadvantage. However, since the two boards operate synchronously with each other using clocks, there is a limit of operation speed, and the retry control upon occurrence of intermittent errors is difficult.